1. Field of the Invention
In general, the present invention relates to a plasma processing method and a plasma processing apparatus. More particularly, the present invention relates to a plasma processing method and a plasma processing apparatus that are suitable for a process to etch a substrate such as a semiconductor wafer by using plasma.
2. Related Background Art
A technology known as a technology for sustaining etching performance is disclosed in Japanese Patent Laid-Open No. H9-129594. As disclosed in the document, this technology provides a capability of control resulting in high etching uniformity, excellent pattern dimensions and a superior pattern cross-sectional shape by controlling a bias voltage in accordance with variations in plasma state detected by adoption of at least one of methods listed below after generating plasma in a gas including a reaction gas by application of a power to a first electrode. The methods are a plasma emission analysis, a mass analysis of a substance in the plasma, a measurement of a self-bias voltage of the plasma and a measurement of an impedance value of the plasma.
In Japanese Patent Laid-Open No. H11-297679, there is disclosed a technology known as a technology for fabricating a device with a fabricated-line dimension up to 1 micron to keep up with miniaturization of semiconductor devices. As disclosed in the document, this technology provides a method for fabricating a surface of a sample whereby the sample is placed on a sample base provided in a vacuum container, a processing gas is supplied to the inside of the container to be converted into plasma, a high-frequency bias with a frequency of at least 100 kHz is applied to the sample base independently of the generation of the plasma, the high-frequency bias is modulated by a frequency in the range 100 Hz to 10 kHz and the voltage of the high-frequency bias is subjected to on-off control of its peak-to-peak voltage Vpp. This peak-to-peak voltage Vpp is greater than the peak-to-peak voltage Vpp of a continuous high-frequency bias required to generate the same etching speed as the on-off control.
With semiconductor devices' speed enhancement in recent years, at the present time, the fabricated-line dimension of LSIs (Large Scale Integrated Circuits) has reached a level of 0.1 microns. Thus, it is necessary to provide a fabrication precision of ±0.01 microns for a device's electrodes and wires.
With an etching apparatus using plasma, on the other hand, there is raised a problem that the fabricated-line dimension slightly varies from wafer to wafer. For example, in an etching apparatus, the plasma is affected by the shape of the inner wall of a vacuum container and other causes. That is, when an Si wafer is etched, a substance obtained as a result of a reaction of Si is stuck to the inner wall and changes the state of the surface of the inner wall. In addition, the stuck substance is later released from the surface of the inner wall. These processes of sticking of such a substance to the inner wall as well as releasing the substance from the wall and other processes change the composition of the plasma. As a result, in sequential wafer processing to process a wafer after another, the fabricated-line width slightly varies from wafer to wafer even if the conditions of the wafer processing such as the gas' flow and pressure are maintained all the time. In the case of a fabricated-line dimension at the 0.1-micron level accompanying device miniaturization in recent years, these dimension variations, which do not raise a problem in the fabricated-line dimension at the 0.5-micron level, cause a problem of a difficulty to satisfy required fabrication precision.
In order to solve this problem, there is provided a method referred as in-situ cleaning. That is, in accordance with this method, a chamber is cleaned after each wafer processing. However, this method causes the throughput to decrease and cannot be said to be effective for all plasma processes. There is also provided another conceivable method whereby processing conditions are changed for each wafer or for each plurality of wafers. As such a method, there is provided a feedback control method like the one described in the Related Background Art.
In the conventional technology whereby a bias voltage is controlled in accordance with various kinds of information obtained from the plasma, etching selectivity changes due to a variation in bias voltage so that this technology is not suitable for a mask and a sample having an underlying film with a small thickness in some cases.
In addition, the conventional technology whereby the voltage of the high-frequency bias is subjected to on-off control does not consider control to turn the voltage of the high-frequency bias on and off in accordance with process variations in the course of processing. Thus, much like the one described above, when the bias voltage (that is, the on-off voltage value Vpp) is controlled in accordance with various kinds of information extracted from the plasma, the effect on the select ratio decreases in comparison with the continuous bias. For the select ratio with respect to a thin underlying film used in a device miniaturized to a level not exceeding 0.1 microns, however, the reduction of the effect on the select ratio still cannot be said to be sufficient.